Extreme ultraviolet (EUV) lithographic integrated circuit (IC) fabrication involves patterning a mask onto an EUV mask blank to create a reticle that is used to etch an integrated circuit (IC) onto silicon wafers. A blank may consist of a low thermal expansion (LET) substrate with a Mo/Si multilayer that reflects 13.5 nm light, which is the wavelength used for exposing the photoresist used for producing the integrated circuit patterns onto the wafers. A patterned reticle is fabricated by printing an absorber layer over the mask blank employing an electron beam writing tool that defines reflective traces corresponding to the desired pattern for IC fabrication. When the patterned reticle is exposed to EUV light, the reflective traces defined by the mask reflect the EUV light onto the silicon wafer, where the reflected light exposes a photoresist with the pattern defined by the mask. After additional develop and etch processes, this creates an integrated circuit on the wafer. Methods and systems are needed to ensure that the reticles (patterned masks) are free from defects to minimize defects in the integrated circuits etched onto the silicon wafers.
The EUV mask blanks inevitably include some defects that can result in errors in the integrated circuits when etched onto the silicon wafers. These defects can occur at multiple levels within the blank. Prior circuit design technologies have not adequately addressed the challenges of defect detection, defect mitigation, and patterned mask repair for defects occurring at multiple levels within blanks in EUV lithographic fabrication of IC wafers. This results in the inefficient fabrication of defective wafers. There is, therefore, a need for more effective methods and systems for defect mitigation in EUV lithographic fabrication of IC wafers.